The performance of computer systems, especially personal computers, has improved dramatically due to the rapid growth in computer architecture design and in particular to the performance of computer memory.
Computer processors and memories, however, have not pursued the same pace of development through the years. Memories are not able to deliver enough response speed to processors. To reduce the gap in speed between the processors and memories, the concept of memory hierarchy was introduced. A memory hierarchy comprises a number of different memory levels, sizes and speeds. The memory located near or inside the processor is usually the smallest and fastest and is commonly referred to as cache memory. Cache memory plays an important role in the computer memory hierarchy. Computer instructions and data which are most likely to be reused are stored temporarily in the cache memory, because the processor can access these instructions or data much faster than accessing them from the slower computer main memory. Cache memory needs to be fast to accommodate the demand of the processor, therefore it is usually constructed from static-type memory or static random access memory (SRAM). SRAM's, however, do not have the memory density of comparable dynamic memories. For an example of an SRAM and additional background in the terminology and specifications for an SRAM, see 1995/1996 SRAM DATA BOOK, pages 1-145 to 1-159, provided by Micron Technology, Inc., the assignee of the present invention, which is incorporated herein by reference.
For the reasons stated above, and for other reasons stated below which will become apparent to those skilled in the art upon reading and understanding the present specification, there is a need in the art for a dynamic random access memory (DRAM) which can be used for cache memory.